1. Field of the Invention
The disclosed technology relates to the field of semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission and a process specially adapted for the manufacture or treatment thereof or of parts thereof.
2. Description of the Related Technology
Assemblies consisting of a plurality of individual semiconductor devices and including semiconductor devices with at least one potential-jump barrier or surface barrier, specially adapted for light emission, are known. Similarly electroluminescent light sources in general, circuit arrangements for light emitting diodes and electric lamps using semiconductor devices as light generating elements are known.
Group III-nitride-based light-emitting diodes are expected to be employed in display and general lighting applications, replacing conventional incandescent and fluorescent lighting sources in near future due to their inherent higher energy efficiency and longer lifetime. In spite of their significant improvements in internal and external quantum efficiencies of the devices, there still remain technical and economical challenges for the LEDs to be competitive in terms of performance characteristics and manufacturing costs. One of the critical technical challenges to be addressed for high-brightness and high-power operations of LEDs is a phenomenon commonly referred to as an efficiency droop, which is observed as a reduction in emission efficiency with increasing injection current under high current density conditions. Nowadays, good LED shows maximum quantum efficiency at 10-20 mA/cm2 and the efficiency continuously decreases at high current density, which is a so called efficiency droop.
Efficiency-droop is a main bottleneck to achieve a high power and high efficiency LED. In an example a high power LED needs to operate at 350 mA or even at 1A. In an example a large LED chip has a feature size of 1×1 mm2 whereas small ones are only 300×300 μm2. Even in the case of large chips with 1×1 mm2 working area, a current density will be 35 and 100 A/cm2, respectively. At such a high current density level, quantum efficiency is significantly reduced.
Various documents recite III-V semiconductor structures.
US 2010264454 (A1) recites that at least partial strain relief in a light emitting layer of a III-nitride light emitting device is provided by configuring the surface on which at least one layer of the device grows such that the layer expands laterally and thus at least partially relaxes. This layer is referred to as the strain-relieved layer. In some embodiments, the light emitting layer itself is the strain-relieved layer, meaning that the light emitting layer is grown on a surface that allows the light emitting layer to expand laterally to relieve strain. In some embodiments, a layer grown before the light emitting layer is the strain-relieved layer. In a first group of embodiments, the strain-relieved layer is grown on a textured surface.
In view of strain relief the above document recites provision of a textured, non regular structure, which is only provided within a certain distance of a light emitting layer. Functionally the n-type posts or polyhedrons in the openings of a mask layer are provided for strain relief, being partially relaxed, such that the material grown in the openings has a lattice constant larger than the lattice constant of the material in contact with the substrate. The light emitting layer (quantum well) is grown over the posts/polyhedrons and replicates their expanded lattice constant. It is not clear if such a structure has further special requirements, e.g. in view of selective/non-selective growth, etc. Thereto a mask is provided, which mask remains present on/in a final structure. The mask occupies surface area which can not be used otherwise. The method recited involves as a consequence also extra steps.
WO 2009111790 (A1) recites a semiconductor emitter, or a precursor therefore. It has a substrate and one or more textured semiconductor layers deposited onto the substrate in a nonpolar orientation. The textured layers enhance light extraction, and the use of non-polar orientation greatly enhances internal quantum efficiency compared to conventional devices. Both the internal and external quantum efficiencies of emitters of the disclosure can be 70-80% or higher. The disclosure provides highly efficient light emitting diodes suitable for solid state lighting.
This document recites a structure that is deposited on a very specific substrate, namely R-plane sapphire. Such a structure is seldom used, and teachings from the document can therefore typically not be applied to methods and products typically used in the field. Further, the textured structure has no further requirements.
US 2010006878 (A1) recites a semiconductor light emitting device having a patterned substrate and a manufacturing method of the same. The semiconductor light emitting device includes a substrate; a first conductivity type nitride semiconductor layer, an active layer and a second conductivity type nitride semiconductor layer sequentially formed on the substrate, wherein the substrate is provided on a surface thereof with a pattern having a plurality of convex portions, wherein out of the plurality of convex portions of the pattern, a distance between a first convex portion and an adjacent one of the convex portions is different from a distance between a second convex portion and an adjacent one of the convex portions.
The above document recites improvement of optical output, by improving a wave guide. The wave guide is improved by providing a rough surface, having a layer bump. Such a layer bump increases a surface area. Thereby injection efficiency is improved, and as a consequence the output is improved.
US 2010155704 (A1) recites a nitride semiconductor light emitting device, and a method of manufacturing the same are disclosed. The nitride semiconductor light emitting device includes a substrate, an n-type nitride semiconductor layer disposed on the substrate and including a plurality of V-shaped pits in a top surface thereof, an active layer disposed on the n-type nitride semiconductor layer and including depressions conforming to the shape of the plurality of V-shaped pits, and a p-type nitride semiconductor layer disposed on the active layer and including a plurality of protrusions on a top surface thereof. Since the plurality of V-shaped pits is formed in the top surface of the n-type nitride semiconductor layer, the protrusions can be formed on the p-type nitride semiconductor layer as an in-situ process. Accordingly, the resistance to ESD, and light extraction efficiency are enhanced.
The V-shaped pits are formed by etching, whereby dislocations in a material become visible. These dislocations are unwanted in general, as they deteriorate quality of a final semiconductor structure/device. Even further, forming these pits is by nature random, as dislocations are formed at random. As in the previous document, the structure is aimed at improving light extraction efficiency, such as by improving a wave guide. Such V-shaped etch-pits eventually seem to appear as bumps or protrusions on a (top) surface.
Certain inventive aspects of this disclosure therefore relates to a method of manufacturing a semiconductor device and the device similar to those in the introduction, which overcomes one or more of the above disadvantages, without jeopardizing functionality and advantages.